![]() Low speed lines going off the PCB should have ferrites for filtering Routing of clock lines and high speed lines should be the shortest and most well-routed traces. The capacitor package size has a bigger impact on its ability to filter higher frequencies than the capacitance value.Decoupling Capacitors should be as close to the power pins as posssible using traces that are as short as possible.Add ground via nears tracks that change ground reference planes.The disks are available with adhesive and are easy to add. Place ferrite disks on top of high speed ICs. Proper terminating resistors at the source. What should the target signal rise/fall times be? Ringing driver and receiver distance > 1/4 the wavelength The series termi-nation resistor should be placed within 1/6th wavelength of the switching speed of the driver. Use series termination resistor and place near the source point.Avoid mutual inductance and mutual capacitance.Make signal spacing larger than the distance to the ground plane.Minimize parallel run lengths between signals Review new footprint sizes and pinout against the datasheetĬheck trace length matching for high speed signals No traces on ground plane breaks - add picturesĮxtra clearance around high speed signalsĮnsure FETs are in a known state at startup (before firmware is driving them)Įxport 3D model and check for interferences Minimize breaks in ground plane (especially from vias) - add pictures Proper layout of decoupling capacitors - add pictures I design boards with microcontrollers so the list is skewed to that end. After many years of designing circuit boards, this is my working list when doing a final review of PCB layout.
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